A demand for increasing network bandwidth imposes a higher requirement on a capacity and integration of a router. A rate of a single line card (LC for short) of a router evolves from 10 gigabits per second (Gbps for short), 40 Gbps, 100 Gbps, or 200 Gbps to 400 Gbps or even higher. A processing capability of a single line card of the router also evolves from 15 mega packets per second (Mpps for short), 60 Mpps, 150 Mpps, or 300 Mpps to 600 Mpps or even higher, which poses a challenge for a rate of a memory of the line card of the router.
Scheduling a packet queue (including packet enqueuing and packet dequeuing) may be implemented by accessing a packet descriptor (PD for short) queue corresponding to the packet queue (including performing a read operation and a write operation on the PD queue). In the prior art, the PD queue is stored in a dynamic random access memory (DRAM for short). Therefore, scheduling the packet queue needs to be implemented by performing a read operation and a write operation on the DRAM. During access to the DRAM, a rate of access to the DRAM is restricted by a property of the DRAM. For example, a rate of the packet queue is 300 MPPS, a row cycle time (tRC for short) of the DRAM is approximately 40-50 nanoseconds (ns for short), and the rate of access to the DRAM is approximately 25 MPPS. Even if the rate of access to the DRAM can be improved to 100 MPPS, a requirement of the rate of the packet queue, that is, 300 MPPS, still cannot be met. In the foregoing technical solutions, a rate of performing a read operation on a PD queue is restricted by a property of a DRAM, which affects dequeuing efficiency of a packet queue.